On Current Strategies for Hardware Acceleration of Digital Image Restoration Filters

Two advanced design methodologies for hardware acceleration of a standard digital image restoration algorithm are explored and compared. The first one is the custom-designed hardware approach, leading to an application-specific integrated circuit (ASIC) implementation. The second one consists of the configurable processor approach, yielding a mixed hardware/software implementation running on a Tensilica Xtensa V (T1050) microprocessor. Both implementations may be embedded as cores in System-on-Chip (SoC) designs. The two methodologies are compared from several standpoints, including implementation size, data throughput, customization, non-recurring engineering and production costs, and flexibility. Key-Words: Image restoration, adaptive Wiener filter, hardware acceleration, SoC design, ASIC, configurable processor, Tensilica Xtensa.